The present invention relates to the field of digital memory circuits, and in particular to parallel addressing and sensing of memory elements in cross-point diode memory arrays.
Many consumer devices are now constructed to generate and/or utilize digital data in increasingly large quantities. Portable digital cameras for still and/or moving pictures, for example, generate large amounts of digital data representing images. Each digital image may require up to several megabytes (MB) of data storage, and such storage must be available in the camera. To provide for this type of data storage application, the storage memory should be relatively low in cost for sufficient capacities of around 10 MB to 1 gigabyte (GB). The storage memory should also be low in power consumption (e.g.  less than  less than 1 Watt) and have relatively rugged physical characteristics to cope with the portable battery powered operating environment. For archival storage, data need only be written to the memory once. Preferably the memory should have a short access time (in the order of milliseconds) and moderate transfer rate (e.g. 20 Mb/s). Preferably, also, the storage memory should be able to be packaged in an industry standard interface module, such as PCMCIA or Compact Flash card.
One form of storage currently used for application in portable devices such as digital cameras is Flash memory. This meets the desired mechanical robustness, power consumption, transfer, and access rate characteristics mentioned above. However, a major disadvantage is that Flash memory remains relatively expensive ($1.50-$2 per MB). Because of the price it is generally unreasonable to use Flash memory storage as an archive device, thus requiring data to be transferred from it to a secondary archival storage.
Magnetic xe2x80x9chard discxe2x80x9d storage can be used for archival storage, even in portable devices. Miniature hard disc drives are available for the PCMCIA type III form factor, offering capacities of up to 1 GB. However, such disc drives are still relatively expensive ($0.5 per MB), at least partially because of the relatively high fixed cost of the disc controller electronics. Miniature hard drives have other disadvantages when compared to Flash memory, such as lower mechanical robustness, higher power consumption (xcx9c2 to 4W), and relatively long access times (xcx9c10 mS).
Removable optical storage discs can similarly be used, and offer one large advantage compared to hard disc. The removable optical media is very inexpensive, for example of the order of $0.03 per MB for Minidisc media. However in most other respects optical disc storage compares poorly with magnetic hard discs including relatively poor power consumption, mechanical robustness, bulk, and access performance.
Another form of archival storage is described in co-pending U.S. patent application Ser. No. 09/875,356, entitled xe2x80x9cNon-Volatile Memoryxe2x80x9d, the disclosure of which is hereby incorporated herein by reference. The memory system disclosed therein aims to provide high capacity write-once memory at low cost for archival storage. This is realized in part by avoiding silicon substrates, minimizing process complexity and lowering areal density. The memory system includes a memory module formed of a laminated stack of integrated circuit layers constructed on plastic substrates. Each layer contains cross-point diode memory array, and sensing of the data stored in the array is carried out from a separate integrated circuit remotely from the memory module. In order to address, read from and write to all of the memory elements in the arrays of the various memory module layers, a multiplexing scheme is required to avoid having too many interconnections between the memory module and the remote sensing circuitry.
In conventional integrated circuits multiplexing is accomplished by logic gates synthesized from transistors. It is undesirable to include transistors in a diode based cross-point memory array because they will add to the required processing thereby increasing the fabrication cost. Some of the additional processing may be incompatible with other materials used in the cross-point array. If plastic substrates or organic semiconductors are used to form the cross-point memory array, for example, they may be destroyed by temperatures required for transistor fabrication, or they could be damaged by certain solvents used in a wet etching process. Recently, researchers at Lawrence Livermore Laboratories have demonstrated the fabrication of thin-film-transistors on a plastic substrate, however the process required is much more complicated, and hence more expensive, than the equivalent process required to fabricate diodes.
Electrostatic micro-relays have been developed for a number of applications including power relays for automotive application, and small signal switching for instrumentation and automatic test equipment. Electrostatic micro-relay systems are described, for example, in Wong, Jo-Ey, et al., xe2x80x9cAn Electrostatically-actuated MEMS Switch for Power Applicationsxe2x80x9d, (Micro Electro-Mechanical Systems, 2000. MEMS ""00. Thirteenth IEEE. 2000), and Zavracky, P. M., et. al., xe2x80x9cMicro-mechanical switches fabricated using nickel surface micro-machiningxe2x80x9d, (Micro-electromechanical Systems, Journal of, 1997.6(1): p3-9). The principle advantages of this technology are low power consumption and simplicity of construction. The processing for these devices is still more significant than that required for a simple diode array, however, particularly if a low contact resistance is required. Other problems associated with electrostatic micro-relays are fatigue life and switching speed.
A third possibility, code-word addressing, includes a number of approaches which have been used to minimize the interconnections to a pixelated display. Such systems are described, for example, in the specification of International Patent Application Publication WO 98/44481, and U.S. Pat. No. 5,034,736. In general code word addressing trades off the ratio of addressing lines to array electrodes and the cross-talk between selected and de-selected electrodes. Although these solutions do not offer log-base-2 reduction in interconnect, they may offer better than 10:1 ratio of electrode to address line, while maintaining a 4:1 cross-talk ratio. Although these solutions are relatively simple to implement, they require a higher number of address lines for a given number of addressed lines than the true multiplexing schemes described previously. A further disadvantage is the cross-talk introduced between addressed and non-addressed memory elements, which makes it difficult to read and write a particular memory element.
In accordance with the principles of the present invention, there is provided an addressing circuit for addressing a cross-point memory array having first and second sets of electrodes from first and second sets of address lines. The addressing circuit has first diode connections between the first set address lines and the first set memory array electrodes, with the first diode connections coupling each memory array electrode in the first set to a respective unique subset of the first set address lines. Second diode connections are provided between the second set address lines and the second set memory array electrodes, with the second diode connections coupling each memory array electrode in the second set to a respective unique subset of the second set address lines. At least one sense line is also provided with diode connections to each of the first set memory array electrodes and/or the second set memory array electrodes.
In the preferred construction of the addressing circuit, the first diode connections comprise diodes elements with anodes coupled to the respective memory array electrodes and cathodes coupled to the respective address lines, and the second diode connections comprise diode elements with cathodes coupled to the respective memory array electrodes and anodes coupled to the respective address lines.
Preferably the cross-point memory array comprises an array of diode based memory elements formed at cross-points of electrodes from the first and second sets, with ends of the electrodes coupled to power supply connections through respective resistive elements. In a preferred embodiment the power supply connections are arranged in power supply striping groups to enable power to be selectively supplied to portions of the cross-point array.
A plurality of cross-point memory arrays can be provided each with respective first diode connections, second diode connections and at least one sense line, and the address lines being coupled in parallel to the plurality of first and second diode connections. With this construction the plurality of memory arrays can be addressed in parallel with outputs therefrom being accessible on through the respective sense lines.
In one form of the invention the addressing circuit includes first and second sense lines, the first sense line having diode connections to each of the first set memory array electrodes, and the second sense line having diode connections to each of the second set memory array electrodes.
The present invention also provides an integrated circuit including at least one cross-point diode memory array and addressing circuit as described above. In a preferred form of the invention, the cross-point diode memory array and addressing circuit are formed in the same fabrication process.
In accordance with the present invention there is also provided a memory circuit including a cross-point memory array having first and second sets of transverse electrodes with respective memory elements formed at the crossing-points of the first and second set electrodes. Each of the memory elements is formed to include, in at least one of its binary states, a diode element. The memory circuit also includes an addressing circuit coupled to the memory array. The addressing circuit has a first set of address lines with first diode connections between the first set address lines and the first set memory array electrodes, with the first diode connections coupling each memory array electrode in the first set to a respective unique subset of the first set address lines. The addressing circuit also has a second set of address lines with second diode connections between the second set address lines and the second set memory array electrodes, with the second diode connections coupling each memory array electrode in the second set to a respective unique subset of the second set address lines. The addressing circuit further includes at least one sense line with diode connections to each of the first set memory array electrodes and/or the second set memory array electrodes.
In the preferred construction of the memory circuit, the diode elements of the first diode connections are oriented differently from the diode elements of the second diode connections with respect to the memory array electrodes and address lines.
Preferably, ends of the memory array electrodes are coupled to power supply connections through respective resistive elements, with the power supply connections being arranged in power supply striping groups to enable power to be selectively supplied to portions of the cross-point array.
According to a preferred embodiment, a memory circuit may comprise a plurality of cross-point memory arrays and respective addressing circuits as described above, wherein the address lines from the respective addressing circuits are coupled in parallel.
In one form of the memory circuit the addressing circuit includes first and second sense lines, the first sense line having diode connections to each of the first set memory array electrodes, and the second sense line having diode connections to each of the second set memory array electrodes.
The first diode connections can be formed at crossing-points of the first address lines and the first set electrodes, and the second diode connections formed at crossing-points of the second address lines and the second set electrodes.
The present invention also provides an integrated circuit having at least one memory circuit as described above. The memory array and addressing circuit can be formed in the same fabrication process. Furthermore, the integrated circuit may be formed on a dielectric substrate surface.
The present invention further provides a memory module comprising a plurality of integrated circuits as described above. In a preferred form of the invention, the memory module is constructed with a plurality of integrated circuits as above described stacked on top of one another.
The present invention further provides a method for addressing a cross-point memory array having first and second sets of electrodes from first and second sets of address lines. The method includes forming first diode connections between the first set address lines and the first set memory array electrodes, with the first diode connections coupling each memory array electrode in the first set to a respective unique subset of the first set address lines. The method also includes forming second diode connections between the second set address lines and the second set memory array electrodes, with the second diode connections coupling each memory array electrode in the second set to a respective unique subset of the second set address lines. At least one sense line is provided with diode connections to each of the first set memory array electrodes and/or the second set memory array electrodes. Addressing of a memory element in the memory array may then be accomplished by applying a predetermined electrical signals to the first and second set address lines to enable detection of the state of the memory element using the at least one sense line.
Preferably the first and second diode connections and the sense line or lines are formed during the same fabrication process as the cross-point memory array.
A plurality of cross-point memory arrays may be formed with respective first and second diode connections and sense lines, wherein the predetermined electrical signals are applied to the address lines of the plurality of memory arrays in parallel to obtain separate memory element sense outputs on the respective sense lines.